From 4ca466e1bb19587ff954ce5508e355ed5a12383e Mon Sep 17 00:00:00 2001
From: Liu Zixian <liuzixian4@huawei.com>
Date: Thu, 10 Nov 2022 19:10:37 +0800
Subject: [PATCH] Suppot for sw arch

Based on version 2.9.1 from wuzx <wuzx1226@qq.com>

Signed-off-by: Liu Zixian <liuzixian4@huawei.com>
---
 config.guess                 | 40 ++++++++++++++++++++++++++++++++++++
 config.sub                   |  1 +
 configure                    |  1 +
 src/base/basictypes.h        |  2 ++
 src/malloc_hook_mmap_linux.h |  3 ++-
 5 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/config.guess b/config.guess
index 7f76b62..abf78f4 100755
--- a/config.guess
+++ b/config.guess
@@ -313,6 +313,36 @@ case $UNAME_MACHINE:$UNAME_SYSTEM:$UNAME_RELEASE:$UNAME_VERSION in
     mips:OSF1:*.*)
 	GUESS=mips-dec-osf1
 	;;
+    sw_64:OSF1:*:*)
+        case $UNAME_RELEASE in
+        *4.0)
+                UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'`
+                ;;
+        *5.*)
+                UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'`
+                ;;
+        esac
+        # According to Compaq, /usr/sbin/psrinfo has been available on
+        # OSF/1 and Tru64 systems produced since 1995.  I hope that
+        # covers most systems running today.  This code pipes the CPU
+        # types through head -n 1, so we only detect the type of CPU 0.
+        SW_64_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^  The sw_64 \(.*\) processor.*$/\1/p' | head -n 1`
+        case "$SW_64_CPU_TYPE" in
+            "SW6A (1621)")
+                UNAME_MACHINE=sw_64sw6a ;;
+            "SW6B (3231)")
+                UNAME_MACHINE=sw_64sw6b ;;
+        esac
+        # A Pn.n version is a patched version.
+        # A Vn.n version is a released version.
+        # A Tn.n version is a released field test version.
+        # A Xn.n version is an unreleased experimental baselevel.
+        # 1.2 uses "1.2" for uname -r.
+        GUESS="$UNAME_MACHINE"-dec-osf"`echo "$UNAME_RELEASE" | sed -e 's/^[PVTX]//' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz`"
+        # Reset EXIT trap before exiting to avoid spurious non-zero exit code.
+        exitcode=$?
+        trap '' 0
+        ;;
     alpha:OSF1:*:*)
 	# Reset EXIT trap before exiting to avoid spurious non-zero exit code.
 	trap '' 0
@@ -976,6 +1006,15 @@ EOF
 	UNAME_MACHINE=aarch64_be
 	GUESS=$UNAME_MACHINE-unknown-linux-$LIBC
 	;;
+    sw_64:Linux:*:*)
+	case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in
+	   SW6A)  UNAME_MACHINE=sw_64sw6a ;;
+	   SW6B)  UNAME_MACHINE=sw_64sw6b ;;
+	esac
+	objdump --private-headers /bin/sh | grep -q ld.so.1
+	if test "$?" = 0 ; then LIBC=gnulibc1 ; fi
+	GUESS="$UNAME_MACHINE"-unknown-linux-"$LIBC"
+	;;
     alpha:Linux:*:*)
 	case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' /proc/cpuinfo 2>/dev/null` in
 	  EV5)   UNAME_MACHINE=alphaev5 ;;
@@ -1512,6 +1551,7 @@ EOF
 	UNAME_MACHINE=`(uname -p) 2>/dev/null`
 	case $UNAME_MACHINE in
 	    A*) GUESS=alpha-dec-vms ;;
+	    S*) GUESS=sw_64-dec-vms ;;
 	    I*) GUESS=ia64-dec-vms ;;
 	    V*) GUESS=vax-dec-vms ;;
 	esac ;;
diff --git a/config.sub b/config.sub
index dba16e8..ef3f539 100755
--- a/config.sub
+++ b/config.sub
@@ -1185,6 +1185,7 @@ case $cpu-$vendor in
 			| alpha | alphaev[4-8] | alphaev56 | alphaev6[78] \
 			| alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] \
 			| alphapca5[67] | alpha64pca5[67] \
+			| sw_64 | sw_64sw6a | sw_64sw6b \
 			| am33_2.0 \
 			| amdgcn \
 			| arc | arceb | arc32 | arc64 \
diff --git a/configure b/configure
index 4e0684d..2953fe4 100755
--- a/configure
+++ b/configure
@@ -19496,6 +19496,7 @@ printf %s "checking how to access the program counter from a struct ucontext...
    pc_fields="$pc_fields uc_mcontext.sc_ip"            # Linux (ia64)
    pc_fields="$pc_fields uc_mcontext.__pc"               # Linux (loongarch64)
    pc_fields="$pc_fields uc_mcontext.pc"               # Linux (mips)
+   pc_fields="$pc_fields uc_mcontext.sc_pc"               # Linux (sw_64)
    pc_fields="$pc_fields uc_mcontext.uc_regs->gregs[PT_NIP]" # Linux (ppc)
    pc_fields="$pc_fields uc_mcontext.__gregs[REG_PC]"  # Linux (riscv64)
    pc_fields="$pc_fields uc_mcontext.psw.addr"         # Linux (s390)
diff --git a/src/base/basictypes.h b/src/base/basictypes.h
index a8c9e1c..0ceec52 100644
--- a/src/base/basictypes.h
+++ b/src/base/basictypes.h
@@ -378,6 +378,8 @@ class AssignAttributeStartEnd {
     // some ARMs have shorter cache lines (ARM1176JZF-S is 32 bytes for example) but obviously 64-byte aligned implies 32-byte aligned
 # elif (defined(__mips__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(128)))
+# elif (defined(__sw_64__))
+#   define CACHELINE_ALIGNED __attribute__((aligned(128)))
 # elif (defined(__aarch64__))
 #   define CACHELINE_ALIGNED __attribute__((aligned(64)))
     // implementation specific, Cortex-A53 and 57 should have 64 bytes
diff --git a/src/malloc_hook_mmap_linux.h b/src/malloc_hook_mmap_linux.h
index c7d8b4b..6de699d 100644
--- a/src/malloc_hook_mmap_linux.h
+++ b/src/malloc_hook_mmap_linux.h
@@ -56,7 +56,8 @@
     || defined(__aarch64__) \
     || defined(__loongarch64) \
     || (defined(_MIPS_SIM) && (_MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32)) \
-    || defined(__s390__) || (defined(__riscv) && __riscv_xlen == 64)
+    || defined(__s390__) || (defined(__riscv) && __riscv_xlen == 64) \
+    || defined(__sw_64__)
 
 static inline void* do_mmap64(void *start, size_t length,
                               int prot, int flags,
-- 
2.36.1

