From 104dce7743c31c73a54095844d704272fa14de69 Mon Sep 17 00:00:00 2001
From: veega2022 <zhuweijia@huawei.com>
Date: Wed, 10 May 2023 18:20:58 +0800
Subject: [PATCH 06/18] fix the number of PCS lane registers in the PCIe
 dumpreg

Traverse the PCS registers of all lanes under the current core.

Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
---
 pcie/func_lib/pcie_func/pcie_reg_dump.c  | 36 +++++++++++-------------
 pcie/func_lib/pcie_func/pcie_reg_dump.h  | 10 +++++++
 pcie/usr_cmd/interface/pcie_common_api.h |  4 +++
 3 files changed, 31 insertions(+), 19 deletions(-)

diff --git a/pcie/func_lib/pcie_func/pcie_reg_dump.c b/pcie/func_lib/pcie_func/pcie_reg_dump.c
index 7d91969..e10ff7e 100644
--- a/pcie/func_lib/pcie_func/pcie_reg_dump.c
+++ b/pcie/func_lib/pcie_func/pcie_reg_dump.c
@@ -108,13 +108,13 @@ struct pcie_dumpreg_info g_reg_table_mac[] = {
 };
 
 struct pcie_dumpreg_info g_reg_table_pcs[] = {
-	{0, "SERDES_STATUS_RPT"},
-	{0, "EBUF_STATUS"},
-	{0, "GEN3_DEC_ENC_STATUS"},
-	{0, "WAKE_STATUS"},
-	{0, "RECV_DET_OR_PWR_CHAGE"},
-	{0, "EQEVAL_STATUS"},
-	{0, "LANE_INTR_STATUS"},
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(SERDES_STATUS_RPT),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(EBUF_STATUS),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(GEN3_DEC_ENC_STATUS),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(WAKE_STATUS),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(RECV_DET_OR_PWR_CHAGE),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(EQEVAL_STATUS),
+	HIKP_PCIE_PCS_LANE_TBL_ENTRY(LANE_INTR_STATUS),
 };
 
 struct pcie_dumpreg_info g_reg_table_iob_tx[] = {
@@ -348,6 +348,13 @@ static void pcie_dumpreg_save_glb_analysis_log(const uint32_t *data, uint32_t da
 		pcie_dumpreg_write_value_to_file(g_reg_table_core_glb[item_i].name,
 						 g_reg_table_core_glb[item_i].val);
 	}
+	/* PCS REG */
+	for (item_i = 0; item_i < HIKP_ARRAY_SIZE(g_reg_table_pcs) &&
+		data_i < data_num; item_i++, data_i++) {
+		g_reg_table_pcs[item_i].val = data[data_i];
+		pcie_dumpreg_write_value_to_file(g_reg_table_pcs[item_i].name,
+						 g_reg_table_pcs[item_i].val);
+	}
 }
 
 static void pcie_dumpreg_save_port_analysis_log(uint32_t *data, uint32_t data_num)
@@ -376,13 +383,6 @@ static void pcie_dumpreg_save_port_analysis_log(uint32_t *data, uint32_t data_nu
 		pcie_dumpreg_write_value_to_file(g_reg_table_mac[item_i].name,
 						 g_reg_table_mac[item_i].val);
 	}
-	/* PCS REG */
-	for (item_i = 0; item_i < HIKP_ARRAY_SIZE(g_reg_table_pcs) &&
-		data_i < data_num; item_i++, data_i++) {
-		g_reg_table_pcs[item_i].val = data[data_i];
-		pcie_dumpreg_write_value_to_file(g_reg_table_pcs[item_i].name,
-						 g_reg_table_pcs[item_i].val);
-	}
 }
 
 static int pcie_dumpreg_write_header_to_file(uint32_t version,
@@ -421,14 +421,12 @@ static int pcie_dumpreg_save_log(uint32_t *data, uint32_t data_num,
 	switch (req_data->level) {
 	case DUMP_GLOBAL_LEVEL:
 		expect_data_num = HIKP_ARRAY_SIZE(g_reg_table_iob_tx) +
-		HIKP_ARRAY_SIZE(g_reg_table_iob_rx) + HIKP_ARRAY_SIZE(g_reg_table_ap_glb) +
-		HIKP_ARRAY_SIZE(g_reg_table_core_glb);
+			HIKP_ARRAY_SIZE(g_reg_table_iob_rx) + HIKP_ARRAY_SIZE(g_reg_table_ap_glb) +
+			HIKP_ARRAY_SIZE(g_reg_table_core_glb) + HIKP_ARRAY_SIZE(g_reg_table_pcs);
 		break;
 	case DUMP_PORT_LEVEL:
 		expect_data_num = HIKP_ARRAY_SIZE(g_reg_table_tl) +
-				  HIKP_ARRAY_SIZE(g_reg_table_dl) +
-				  HIKP_ARRAY_SIZE(g_reg_table_mac) +
-				  HIKP_ARRAY_SIZE(g_reg_table_pcs);
+			HIKP_ARRAY_SIZE(g_reg_table_dl) + HIKP_ARRAY_SIZE(g_reg_table_mac);
 		break;
 	default:
 		Err("PCIe DUMPREG", "check dump level failed.\n");
diff --git a/pcie/func_lib/pcie_func/pcie_reg_dump.h b/pcie/func_lib/pcie_func/pcie_reg_dump.h
index 1993c1f..4ec1909 100644
--- a/pcie/func_lib/pcie_func/pcie_reg_dump.h
+++ b/pcie/func_lib/pcie_func/pcie_reg_dump.h
@@ -20,6 +20,16 @@
 #define MAX_STR_LEN 80
 #define PCIE_DUMPREG_LOGFILE_NAME "pcie_dumpreg"
 
+#define HIKP_PCIE_PCS_LANE_TBL_ENTRY(name) \
+	{0, STR(CONTACT(name, _00))}, {0, STR(CONTACT(name, _01))}, \
+	{0, STR(CONTACT(name, _02))}, {0, STR(CONTACT(name, _03))}, \
+	{0, STR(CONTACT(name, _04))}, {0, STR(CONTACT(name, _05))}, \
+	{0, STR(CONTACT(name, _06))}, {0, STR(CONTACT(name, _07))}, \
+	{0, STR(CONTACT(name, _08))}, {0, STR(CONTACT(name, _09))}, \
+	{0, STR(CONTACT(name, _10))}, {0, STR(CONTACT(name, _11))}, \
+	{0, STR(CONTACT(name, _12))}, {0, STR(CONTACT(name, _13))}, \
+	{0, STR(CONTACT(name, _14))}, {0, STR(CONTACT(name, _15))}
+
 enum pcie_dump_level {
 	DUMP_GLOBAL_LEVEL = 1,
 	DUMP_PORT_LEVEL = 2,
diff --git a/pcie/usr_cmd/interface/pcie_common_api.h b/pcie/usr_cmd/interface/pcie_common_api.h
index f6541bd..9809575 100644
--- a/pcie/usr_cmd/interface/pcie_common_api.h
+++ b/pcie/usr_cmd/interface/pcie_common_api.h
@@ -17,6 +17,10 @@
 #include <stdint.h>
 #include <stdio.h>
 
+#define CONTACT(x, y) x##y
+#define STR_INTER(x) #x
+#define STR(x) STR_INTER(x)
+
 struct print_info {
 	char *buff;
 	size_t buff_size;
-- 
2.25.1

