Changes to be committed:
new file: 0094-libhns-Fix-the-max_inline_data-value.patch
new file: 0095-libhns-Adapt-UD-inline-data-size-for-UCX.patch
new file: 0096-libhns-Fix-wrong-order-of-spin_unlock-in-modify_qp.patch
modified: rdma-core.spec
Signed-off-by: Xinghai Cen <cenxinghai@h-partners.com>
The sl and src_qpn fields in recv-WC are not filled when the QP is UD
and has an SRQ. Here fix it.
In addition, UD QP does not support RQ INLINE and CQE INLINE features.
Reorder the related if-else statements to reduce the number of
conditional checks in IO path.
Signed-off-by: Xinghai Cen <cenxinghai@h-partners.com>
driver inclusion
category: bugfix
bugzilla: https://gitee.com/src-openeuler/rdma-core/issues/IBOR88
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Fixes several bugs for hns:
libhns: Add the parsing of mac type in RoH mode
Signed-off-by: Dazhao Lao <laodazhao@huawei.com>
Two bugfixes in post_send flow:
libhns: Fix out-of-order issue of requester when setting FENCE
libhns: Fix reference to uninitialized cq pointer
Signed-off-by: huwentao <huwentao19@h-partners.com>
driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IALOAP
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Fixes several bugs for hns:
libhns: Fix overwritten SL in DSCP mode
libhns: Support returning the final value of SL configuration
libhns: Fix memory leakage when DCA is enabled
libhns: Fix the exception branch of wr_start() is not locked
Signed-off-by: Xinghai Cen <cenxinghai@h-partners.com>
Currently, there is a repeated judgement in check_qp_congest_type
whenever enable LDCP or HC3, the congest type flags all will be set
on LDCP.
This patch fixes this bug and replace a corrupt patch--0077, which
has a change that directly acts on patch but not code. This act
will disrupt the patch format.
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
(cherry picked from commit 4a7be9bb67fa9e61cc21625e448369783982e2b7)
Currently, if compiler does not support SVE, hns_roce_sve_write512() will
be a empty function, which means that this doorbell will be missed when
HNS_ROCE_QP_CAP_SVE_DIRECT_WQE is set in qp flag.
This patch ensures that driver will at least generate the DB regardless
of whether SVE DWQE is supported or not.
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
Correct the return of error code, add init of pthread spinlock and mutex
judgement, remove a repeated init of pthread lock init, fix owner bit
when SQ wrqps.
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
Currently the QPC state in HW is modified inside the critical section of
spinlock but the ibv_qp state is modified outside. There will be a short
period when QPC state has been modified to err with ibv_qp state still
remaining RTS. WQEs during this period will still be post-send by RTS-state
ibv_qp but then dropped by err-state HW with no flush CQEs generated.
To fix this problem, the QPC state in HW and ibv_qp state should be both
modified to err inside the critical section of spinlock.
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
The issues mainly lies in the memory empty check, variable range
inconsistency, parameter verification, and print format.
Signed-off-by: Luoyouming <luoyouming@huawei.com>
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
As dmac is already resolved in kernel while creating AH, there is no
need to repeat the resolving in userspace. Prioritizes getting dmac
from kernel driver, unless kernel driver didn't response one.
Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com>
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
For RDMA over UBLink, MAC Layer if replaced by UBLink, and thus the
MAC addr is not nedded. So skip the MAC addr resolving for this mode.
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com>
Signed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8A08Z
Compared with normal doorbell, using record doorbell can shorten the
process of ringing the doorbell and reduce the latency.
Signed-off-by: Yangyang Li <liyangyang20@huawei.com>
Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com>
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
In order to improve performance, we allow user-mode drivers to use a
larger page size to allocate WQE buffers, thereby reducing the latency
introduced by HW page switching. User-mode drivers will be allowed to
allocate WQE buffers between 4K to system page size. During
ibv_create_qp(), the driver will dynamically select the appropriate page
size based on ibv_qp_cap, thus reducing memory consumption while improving
performance.
Signed-off-by: Ran Zhou <zhouran10@h-partners.com>
1.libhns: Support reporting wc as software mode
2.libhns: return error when post send in reset state
3.libhns: separate the initialization steps of lock
4.libhns: assign doorbell to zero when allocate it
5.libhns: Fix missing reset notification
Signed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
According to Annex17_RoCEv2 (A17.4.5.2), for RoCEv2 UD, a CQE should
carry a flag that indicates if the received frame is an IPv4, IPv6 or
RoCE packet. But currently, the values of the flag corresponding to
these packet types haven't been defined yet in WC.
In UCX, 'sl' in ibv_wc for UD is used as the packet type flag, and the
packet type values have already been defined in the UCX patch of
ed28845b88
Therefore, to adapt UCX, add a create flag to hnsdv_create_qp() to allow
users to choose whether they use 'sl' in ibv_wc as service level or
packet type for UD. For the latter, obtain and translate the packet type
from CQE and fill it to 'sl' in ibv_wc.
Singed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
(cherry picked from commit e102d4c9aa2992c125b26ad5cc237ae002bc6541)
1.Fix the owner bit error of sq in new io
2.Fix incorrect post-send with direct wqe of
3.Add a judgment to the congestion control algorithm
Singed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
(cherry picked from commit 092143ba858a7aba0630fadd416faa2a4e7eaf06)
1. The hns hardware logic requires wr->num_sge to be 1 when
performing atomic operations. The code does not judge this
condition, and the current patch adds this constraint.
2. In the sq inline scenario, when num_sge in post_send is not 1, sge
array appears in the for loop without rotation and directly copy
out of bounds.
3. Currently local invalidate operation don't work properly.
Disable it for the time being.
HIP08 and HIP09 hardware does not support this feature, so
delete the associated code.
Signed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
Some Kunpeng SoCs do not support the DWQE through NEON
instructions. In this case, the IO path works normally,
but the performance will deteriorate.
For these SoCs that do not support NEON DWQE, they support
DWQE through SVE instructions. This patch supports SVE DWQE
to guarantee the performance of these SoCs. In addition, in
this scenario, DWQE only supports acceleration through SVE's
ldr and str instructions. Other load and store instructions
also cause performance degradation.
Signed-off-by: Juan Zhou <zhoujuan51@h-partners.com>
